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Micropower, Rail-to-Rail Input Current Sense Amplifier with Voltage Output
ISL28005
The ISL28005 is a micropower, uni-directional high-side and low-side current sense amplifier featuring a proprietary rail-to-rail input current sensing amplifier. The ISL28005 is ideal for high-side current sense applications where the sense voltage is usually much higher than the amplifier supply voltage. The device can be used to sense voltages as high as 28V when operating from a supply voltage as low as 2.7V. The micropower ISL28005 consumes only 50A of supply current when operating from a 2.7V to 28V supply. The ISL28005 features a common-mode input voltage range from 0V to 28V. The proprietary architecture extends the input voltage sensing range down to 0V, making it an excellent choice for low-side ground sensing applications. The benefit of this architecture is that a high degree of total output accuracy is maintained over the entire 0V to 28V common mode input voltage range. The ISL28005 is available in fixed (100V/V, 50V/V and 20V/V) gains in the space saving 5 Ld SOT-23 package. The parts operate over the extended temperature range from -40C to +125C.
ISL28005
Features
* Low Power Consumption . . . . . . . . . . . 50A,Typ * Supply Range. . . . . . . . . . . . . . . . . . 2.7V to 28V * Wide Common Mode Input . . . . . . . . . 0V to 28V * Fixed Gain Versions - ISL28005-100 . . . . . . . . . . . . . . . . . . . 100V/V - ISL28005-50. . . . . . . . . . . . . . . . . . . . . 50V/V - ISL28005-20. . . . . . . . . . . . . . . . . . . . . 20V/V * Operating Temperature Range . . -40C to +125C * Package . . . . . . . . . . . . . . . . . . . . .5 Ld SOT-23
Applications*(see page 13)
* Power Management/Monitors * Power Distribution and Safety * DC/DC, AC/DC Converters * Battery Management /Charging * Automotive Power Distribution
Related Literature*(see page 13)
* See AN1531 for "ISL28005 Evaluation Board User's Guide"
Typical Application
SENSE +12VDC RSENSE +12VDC OUTPUT + RSENSE +5VDC
ISL28005
High-Side And Low-Side Threshold Voltage
1.8 1.6 1.4 1.2 VOLTS (V) 1.0 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 1.4 1.6 1.8 2.0 VRS+ ISENSE +12VDC +5VDC OUTPUT
SENSE +5VDC
VTH(L-H) = 1.52V VTH(H-L) = 1.23V
+
+5VDC ISENSE +5VDC +1.0VDC OUTPUT ISENSE +1.0VDC
ISL28005
VOUT (G=100) G100, VOUT = 1V G50, VOUT = 500mV G20, VOUT = 200mV
SENSE +1.0VDC MULTIPLE OUTPUT POWER SUPPLY GND RSENSE +5VDC
+
ISL28005
September 16, 2010 FN6973.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL28005
Block Diagram
VCC I = 2.86A VSENSE RS+ R1 gmHI HIGH-SIDE AND LOW-SIDE SENSING
RSR2 + 1.35V R3 OUT Rf
gmLO VSENSE
R5
Rg
IMIRROR R4
GND
Pin Configuration
ISL28005 (5 LD SOT-23) TOP VIEW
GND 1 OUT 2 VCC 3 FIXED GAIN 4 RS+ 5 RS-
Pin Descriptions
ISL28005 PIN (5 LD SOT-23) NAME 1 2 3 4 5 GND OUT VCC RS+ RSDESCRIPTION Power Ground Amplifier Output Positive Power Supply Sense Voltage Non-inverting Input Sense Voltage Inverting Input
VCC RS-
CAPACITIVELY COUPLED ESD CLAMP
OUT
RS+ GND
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Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL28005FH100Z-T7 ISL28005FH100Z-T7A ISL28005FH50Z-T7 ISL28005FH50Z-T7A ISL28005FH20Z-T7 ISL28005FH20Z-T7A ISL28005FH-100EVAL1Z ISL28005FH-50EVAL1Z ISL28005FH-20EVAL1Z NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28005. For more information on MSL please see techbrief TB363. 4. The part marking is located on the bottom of the part. GAIN 100V/V 100V/V 50V/V 50V/V 20V/V 20V/V PART MARKING (Note 4) BDEA BDEA BDDA BDDA BDCA BDCA PACKAGE Tape & Reel (Pb-Free) 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 PKG. DWG. # P5.064A P5.064A P5.064A P5.064A P5.064A P5.064A
100V/V Evaluation Board 50V/V Evaluation Board 20V/V Evaluation Board
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Absolute Maximum Ratings
Max Supply Voltage . . . . . . . . . . . . . . . . Max Differential Input Current . . . . . . . . Max Differential Input Voltage . . . . . . . . . Max Input Voltage (RS+, RS-) . . . . . . . . . Max Input Current for Input Voltage Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 5 Ld SOT-23 (Notes 5, 6) . . . . . . . 190 90 Maximum Storage Temperature Range . . . -65C to +150C Maximum Junction Temperature (TJMAX) . . . . . . . . . +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . -40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the "case temp" location is taken at the package top center.
Electrical Specifications VCC = 12V, VRS+ = 0V to 28V, VSENSE = 0V, RLOAD = 1M, TA = +25C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40C to +125C. Temperature data established by characterization. CONDITIONS VCC = VRS+ = 12V, VS = 20mV to = 100mV VCC = 12V, VRS+ = 0.2V, VS = 20mV, VS = 100mV IRS+, IRS IRS+ Leakage Current Gain = 100 + Input Bias Current VCC = 0V, VRS+ = 28V VRS+ = 2V, VSENSE = 5mV VRS+ = 0V, VSENSE = 5mV Gain = 50, Gain = 20 +Input Bias Current VRS+ = 2V, VSENSE = 5mV VRS+ = 0V, VSENSE = 5mV IRS Input Bias Current VRS+ = 2V, VSENSE = 5mV VRS+ = 0V, VSENSE = 5mV CMRR PSRR VFS G Common Mode Rejection Ratio Power Supply Rejection Ratio Full-scale Sense Voltage Gain (Note 8) VRS+ = 2V to 28V VCC = 2.7V to 28V, VRS+ = 2V VCC = 28V, VRS+ = 0.2V, 12V ISL28005-100 ISL28005-50 ISL28005-20 -125 -130 105 90 200 100 50 20 -700 -840 -500 -600 MIN (Note 7) -500 -500 -3 -3.3 TYP 60 -1.2 0.041 4.7 -425 4.7 -432 5 -45 115 105 50 75 6 8 MAX (Note 7) 500 500 3 3.3 1.2 1.5 6 7
PARAMETER VOS
DESCRIPTION Input Offset Voltage (Notes 8, 9)
UNIT V mV A A nA A nA nA nA dB dB mV V/V V/V V/V
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Electrical Specifications VCC = 12V, VRS+ = 0V to 28V, VSENSE = 0V, RLOAD = 1M, TA = +25C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40C to +125C. Temperature data established by characterization. (Continued) CONDITIONS VCC = VRS+ = 12V, VSENSE = 20mV to 100mV VCC = 12V, VRS+ = 0.1V, VSENSE = 20mV to 100mV Gain = 50, Gain = 20 Gain Accuracy (Note 10) VCC = VRS+ = 12V, VSENSE = 20mV to 100mV VCC = 12V, VRS+ = 0.1V, VSENSE = 20mV to 100mV VOA Gain = 100 Total Output Accuracy (Note 11) VCC = VRS+ = 12V, VSENSE = 100mV VCC = 12V, VRS+ = 0.1V, VSENSE = 100mV Gain = 50, Gain = 20 Total Output Accuracy (Note 11) VCC = VRS+ = 12V, VSENSE = 100mV VCC = 12V, VRS+ = 0.1V, VSENSE = 100mV VOH Output Voltage Swing, High VCC - VOUT Output Voltage Swing, Low VOUT Output Resistance IO = -500A, VCC = 2.7V VSENSE = 100mV VRS+ = 2V IO = 500A, VCC = 2.7V VSENSE = 0V, VRS+ = 2V VCC = VRS+ = 12V, VSENSE = 100mV IOUT = 10A to 1mA VCC = VRS+ = 5V, RL = 10 VCC = VRS+ = 5V, RL = 10 VRS+ > 2V, VSENSE = 5mV VRS+ > 2V, VSENSE = 5mV Guaranteed by PSRR Pulse on RS+ pin, VOUT = 8VP-P (see Figure 15) Pulse on RS+ pin, VOUT = 8VP-P (see Figure 15) Pulse on RS+ pin, VOUT = 3.5VP-P (see Figure 15) VRS+ = 12V, 0.1V, VSENSE = 100mV VRS+ = 12V, 0.1V, VSENSE = 100mV VRS+ = 12V, 0.1V, VSENSE = 100mV 2.7 0.58 0.76 -2.5 -2.7 -6 -7 -1.41 39 -2 -3 -3 -4 -2.5 -2.7 -1.25 2.5 2.7 6 7 50 -0.31 MIN (Note 7) -2 -3 -0.25 2 3 3 4 2.5 2.7 TYP MAX (Note 7) 2 3
PARAMETER GA
DESCRIPTION Gain = 100 Gain Accuracy (Note 10)
UNIT % % % % % % % % mV
VOL ROUT
30 6.5
50
mV
ISC+ ISCIS
Short Circuit Sourcing Current Short Circuit Sinking Current Gain = 100 Supply Current Gain = 50, 20 Supply Current
4.8 8.7 50 50 59 62 62 63 28
mA mA A A V V/s
VCC SR
Supply Voltage Gain = 100 Slew Rate
Gain = 50 Slew Rate
0.58
0.67
V/s
Gain = 20 Slew Rate
0.50
0.67
V/s
BW-3dB
Gain = 100 -3dB Bandwidth Gain = 50 -3dB Bandwidth Gain = 20 -3dB Bandwidth
110 160 180
kHz kHz kHz
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Electrical Specifications VCC = 12V, VRS+ = 0V to 28V, VSENSE = 0V, RLOAD = 1M, TA = +25C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40C to +125C. Temperature data established by characterization. (Continued) CONDITIONS VCC = VRS+ = 12V, VOUT = 10V step, VSENSE >7mV VCC = VRS+ = 0.2V, VOUT = 10V step, VSENSE >7mV Capacitive-Load Stability ts Power-up No sustained oscillations MIN (Note 7) TYP 15 20 300 15 50 10 MAX (Note 7)
PARAMETER ts
DESCRIPTION Output Settling Time to 1% of Final Value
UNIT s s pF s s s
Power-Up Time to 1% of Final Value VCC = VRS+ = 12V, VSENSE = 100mV VCC = 12V, VRS+ = 0.2V VSENSE = 100mV Saturation Recovery Time VCC = VRS+ = 12V, VSENSE = 100mV, overdrive
NOTES: 7. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. DEFINITION OF TERMS: * VSENSEA = VSENSE @100mV * VSENSEB = VSENSE @20mV * VOUTA = VOUT@VSENSEA=100mV * VOUTB = VOUT@VSENSEB=20mV V OUT A - V OUT B * G = GAIN = ------------------------------------------------------------- V SENSE A - V SENSE B V OUT A 9. VOS is extrapolated from the gain measurement. V OS = V SENSE A - ------------------G G MEASURED - G EXPECTED 10. % Gain Accuracy = GA = ------------------------------------------------------------------------------ x 100 G EXPECTED VOUT MEASURED - VOUT EXPECTED 11. Output Accuracy % VOA = --------------------------------------------------------------------------------------------------------- x 100 where VOUT = VSENSE X GAIN and VSENSE = 100mV VOUT EXPECTED
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Typical Performance Curves
12 GAIN 100 10 8 VOUT (V)
Vcc = 12V, RL = 1M, unless otherwise specified.
12 GAIN 100 10 8 VOUT (V) 6 4 2 0
6 4 2 0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
TIME (s)
40 50 60 TIME (s)
70
80
90
100
FIGURE 1. LARGE SIGNAL TRANSIENT RESPONSE VRS+ = 0.2V, VSENSE = 100mV
FIGURE 2. LARGE SIGNAL TRANSIENT RESPONSE VRS+ =12V, VSENSE = 100mV
1.8 1.6 1.4 1.2 VOLTS (V) 1.0 0.8 0.6 0.4 0.2 0 0
VRS+
2.4 VRS+ 2.0 VTH(L-H) = 1.52V VRS+ (V) VTH(H-L) = 1.23V 1.6 1.2 0.8 G100, VOUT = 1V G50, VOUT = 500mV G20, VOUT = 200mV 0.4 0 VOUT (G = 100) RL = 1M VCC = 12V
12 10 8 6 4 2 0 2.0 VOUT (V)
VOUT (G = 100)
G100, VOUT = 2V G50, VOUT = 1V G20, VOUT = 400mV 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 1.4 1.6 1.8
0.2
0.4
0.6
0.8 1.0 1.2 TIME (ms)
1.4
1.6
1.8
2.0
FIGURE 3. HIGH-SIDE and LOW-SIDE THRESHOLD VOLTAGE VRS+(L-H) and VRS+(H-L), VSENSE = 10mV
FIGURE 4. VOUT vs VRS+, VSENSE = 20mV TRANSIENT RESPONSE
0.2 VOA PERCENT ACCURACY (%) 0.0 -0.2 +25C -0.4 -0.6 -0.8 +125C -1.0 1 10 100 IOUT(A) 1m -40C
GAIN 100
45 35 25 GAIN (dB) 15 5 -5 VCC = 12V -15 V SENSE = 100mV -25 AV = 100 RL = 1M -35 10 100 VRS+ = 12V VRS+= 100mV GAIN 100
10m
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 5. NORMALIZED VOA vs IOUT
FIGURE 6. GAIN vs FREQUENCY VRS+= 100mV/12V, VSENSE = 100mV, VOUT = 250mVP-P
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Typical Performance Curves
0.2 VOA PERCENT ACCURACY (%) 0.0 -0.2 GAIN 50
Vcc = 12V, RL = 1M, unless otherwise specified. (Continued)
45 35 25 GAIN (dB) 15 5 -5 VCC = 12V -15 V SENSE = 100mV A = 100 -25 V RL = 1M -35 10 100 VRS+ = 12V VRS+= 100mV GAIN 50
-0.4 -0.6 -0.8
+25C
-40C
+125C -1.0 1 10 100 IOUT(A) 1m 10m
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 7. NORMALIZED VOA vs IOUT
FIGURE 8. GAIN vs FREQUENCY VRS+=100mV/12V, VSENSE = 100mV, VOUT = 250mVP-P
0.2 VOA PERCENT ACCURACY (%) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 1 +125C 10 100 IOUT(A) 1m
GAIN 20
45 35 25 GAIN (dB)
GAIN 20
-40C +25C
15 5 -5 VCC = 12V -15 V SENSE = 100mV A = 100 -25 V RL = 1M -35 10 100 VRS+= 100mV
VRS+ = 12V
10m
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 9. NORMALIZED VOA vs IOUT
FIGURE 10. GAIN vs FREQUENCY VRS+=100mV/12V, VSENSE = 100mV, VOUT = 250mVP-P
Test Circuits and Waveforms
VCC VR1 R1 + + VRS+ VSENSE GND 1M RL VOUT RS+ RSOUT + VRS+ VR2 VSENSE R2 GND 1M RL VOUT + RS+ RSOUT VCC
FIGURE 11. IS, VOS, VOA, CMRR, PSRR, GAIN ACCURACY
FIGURE 12. INPUT BIAS CURRENT, LEAKAGE CURRENT
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Test Circuits and Waveforms (Continued)
VCC RS+ VRS+ VRSPULSE GENERATOR RSGND 1M RL VOUT VRS+ SIGNAL GENERATOR OUT VSENSE VCC RS+ RSGND 1M RL VOUT
OUT
FIGURE 13. SLEW RATE, ts, SATURATION RECOVERY TIME
FIGURE 14. GAIN vs FREQUENCY
VCC RS+ VRS+ RSGND 1M RL VOUT
OUT
PULSE GENERATOR
FIGURE 15. SLEW RATE
Applications Information
Functional Description
The ISL28005-20, ISL28005-50 and ISL28005-100 are single supply, uni-directional current sense amplifiers with fixed gains of 20V/V, 50V/V and 100V/V respectively. The ISL28005 is a 2-stage amplifier. Figure 16 shows the active circuitry for high-side current sense applications where the sense voltage is between 1.35V to 28V. Figure 17 shows the active circuitry for ground sense applications where the sense voltage is between 0V to 1.35V. The first stage is a bi-level trans-conductance amp and level translator. The gm stage converts the low voltage drop (VSENSE) sensed across an external milli-ohm sense resistor, to a current (@ gm = 21.3A/V). The trans-conductance amplifier forces a current through R1 resulting to a voltage drop across R1 that is equal to the sense voltage (VSENSE). The current through R1 is mirrored across R5 creating a ground-referenced voltage at the input of the second amplifier equal to VSENSE.
The second stage is responsible for the overall gain and frequency response performance of the device. The fixed gains (20, 50, 100) are set with internal resistors Rf and Rg. The only external component needed is a current sense resistor (typically 0.001 to 0.01, 1W to 2W). The transfer function is given in Equation 1.
V OUT = GAIN x ( I S R S + V OS ) (EQ. 1)
The input gm stage derives its ~2.86A supply current from the input source through the RS+ terminal as long as the sensed voltage at the RS+ pin is >1.35V and the gmHI amplifier is selected. When the sense voltage at RS+ drops below the 1.35V threshold, the gmLO amplifier kicks in and the gmLO output current reverses, flowing out of the RS- pin.
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VCC OPTIONAL FILTER CAPACITOR I = 2.86A VSENSE RS+ IS + RSR2 + OPTIONAL TRANSIENT PROTECTION 1.35V R3 OUT Rf RS VSENSE R1 gmHI HIGH-SIDE SENSING VRS+= 2V TO 28V VCC = 2V TO 28V
gmLO `VSENSE
R5
Rg
LOAD R4
IMIRROR GND
FIGURE 16. HIGH-SIDE CURRENT DETECTION
VCC OPTIONAL FILTER CAPACITOR I = 2.86A VSENSE RS+ IS + RSR2 + OPTIONAL TRANSIENT PROTECTION 1.35V R3 VCC OUT Rf RS VSENSE R1 gmHI LOW-SIDE SENSING VRS+= 0V TO 2V VCC = 2V TO 28V
gmLO
R5 `VSENSE
Rg
LOAD R4
IMIRROR
GND
FIGURE 17. LOW-SIDE CURRENT DETECTION
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Hysteretic Comparator
The input trans-conductance amps are under control of a hysteretic comparator operating from the incoming source voltage on the RS+ pin (see Figure 18). The comparator monitors the voltage on RS+ and switches the sense amplifier from the low-side gm amp to the high-side gm amplifier whenever the input voltage at RS+ increases above the 1.35V threshold. Conversely, a decreasing voltage on the RS+ pin, causes the hysteric comparator to switch from the high-side gm amp to the low-side gm amp as the voltage decreases below 1.35V. It is that low-side sense gm amplifier that gives the ISL28005 the proprietary ability to sense current all the way to 0V. Negative voltages on the RS+ or RS- are beyond the sensing voltage range of this amplifier.
0.5 0.4 0.3 ACCURACY (%) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 VRS+ (V) 1.4 1.6 1.8 2.0
flowing through the input while adding only an additional 13V (worse case over-temperature) of VOS. Refer to the following formula: ((RP x IRS-) = (100 x 130nA) = 13V) Switching applications can generate voltage spikes that can overdrive the amplifier input and drive the output of the amplifier into the rails, resulting in a long overload recovery time. Capacitors CM and CD filter the common mode and differential voltage spikes.
Error Sources
There are 3 dominant error sources: gain error, input offset voltage error and Kelvin voltage error (see Figure 19). The gain error is dominated by the internal resistance matching tolerances. The remaining errors appear as sense voltage errors at the input to the amplifier. They are VOS of the amplifier and Kelvin voltage errors. If the transient protection resistor is added, an additional VOS error can result from the IxR voltage due to input bias current. The limiting resistor should only be added to the RS- input, due to the high-side gm amplifier (gmHI) sinking several micro amps of current through the RS+ pin.
Layout Guidelines
Kelvin Connected Sense Resistor
The source of Kelvin voltage errors is illustrated in Figure 19. The resistance of 1/2 oz. copper is ~1m per square with a TC of ~3900ppm/C (0.39%/C). When you compare this unwanted parasitic resistance with the total of 1m to 10m resistance of the sense resistor, it is easy to see why the sense connection must be chosen very carefully. For example, consider a maximum current of 20A through a 0.005 sense resistor, generating a VSENSE = 0.1 and a full scale output voltage of 10V (G = 100). Two side contacts of only 0.25 square per contact puts the VSENSE input about 0.5 x 1m away from the resistor end capacitor. If only 10A the 20A total current flows through the kelvin path to the resistor, you get an error voltage of 10mV (10A x 0.5sq x 0.001/sq. = 10mV) added to the 100mV sense voltage for a sense voltage error of 10% (0.110V - 0.1)/0.1V)x 100.
FIGURE 18. GAIN ACCURACY vs VRS+ = 0V TO 2V
Typical Application Circuit
Figure 20 shows the basic application circuit and optional protection components for switched-load applications. For applications where the load and the power source is permanently connected, only an external sense resistor is needed. For applications where fast transients are caused by hot plugging the source or load, external protection components may be needed. The external current limiting resistor (RP) in Figure 20 may be required to limit the peak current through the internal ESD diodes to < 20mA. This condition can occur in applications that experience high levels of in-rush current causing high peak voltages that can damage the internal ESD diodes. An RP resistor value of 100 will provide protection for a 2V transient with the maximum of 20mA
CURRENT SENSE Resistor Current Sense RESISTOR
Non-uniform NON-UNIFORM CURRENT Flow Current FLOW CURRENTIn Current IN
1m TO 10m 1 to 10mO
Copper Trace 1/2 Oz COPPER TRACE 1m /SQ 30mO/Sq.
CURRENT OUT
Current Out
PC Board PC BOARD
KELVINV SS CONTACTS Kelvin V Contacts
FIGURE 19. PC BOARD CURRENT SENSE KELVIN CONNECTION
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2.7VDC TO 28VDC
VCC
I = 2.86A
RS+
(1m RS TO 0.1)
CD
gmHI
RSCM RP + 0.1VDC TO 28VDC 1.35V
+ -
OUT
gmLO
LOAD
GND
FIGURE 20. TYPICAL APPLICATION CIRCUIT
Overall Accuracy (VOA %)
VOA is defined as the total output accuracy Referred-to-Output (RTO). The output accuracy contains all offset and gain errors, at a single output voltage. Equation 2 is used to calculate the % total output accuracy.
V OUT actual - V OUT exp ected V OA = 100 x ------------------------------------------------------------------------------------ V OUT exp ected (EQ. 2)
where: * PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) * PDMAX for each amplifier can be calculated using Equation 5:
V OUTMAX PD MAX = V S x I qMAX + ( V S - V OUTMAX ) x --------------------------R
L
(EQ. 5)
where VOUT Actual = VSENSE x GAIN Example: Gain = 100, For 100mV VSENSE input we measure 10.1V. The overall accuracy (VOA) is 1% as shown in Equation 3.
10.1 - 10 V OA = 100 x ----------------------- = 1percent 10 (EQ. 3)
where: * TMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of 1 amplifier * VCC = Total supply voltage * IqMAX = Maximum quiescent supply current of 1 amplifier * VOUTMAX = Maximum output voltage swing of the application RL = Load resistance
Power Dissipation
It is possible to exceed the +150C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 4:
T JMAX = T MAX + JA xPD MAXTOTAL (EQ. 4)
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 9/2/10 5/12/10 REVISION FN6973.3 FN6973.2 CHANGE Added -T7A tape and reel package options to Ordering Information Table for all packages. Added Note 4 to Part Marking Column in "Ordering Information" on page 3. Corrected hyperlinks in Notes 1 and 3 in "Ordering Information" on page 3. Corrected ISL28005 hyperlink in "Products" on page 13. Added Eval boards to ordering info. Added "Related Literature*(see page 13)" on page 1 Updated Package Drawing Number in the "Ordering Information" on page 3 from MDP0038 to P50.64A. Revised package outline drawing from MDP0038 to P5.064A on page 14. MDP0038 package contained 2 packages for both the 5 and 6 Ld SOT-23. MDP0038 was obsoleted and the packages were separated and made into 2 separate package outline drawings; P5.064A and P6.064A. Changes to the 5 Ld SOT-23 were to move dimensions from table onto drawing, add land pattern and add JEDEC reference number. FN6973.1 -Page1: Edited last sentence of paragraph 2. Moved order of GAIN listings from 20, 50, 100 to 100, 50, 20 in the 3rd paragraph. Under Features ....removed "Low Input Offset Voltage 250V,max" Under Features .... moved order of parts listing from 20, 50, 100 (from top to bottom) to 100, 50, 20. -Page 3: Removed coming soon on ISL28005FH50Z and ISL28005FH20Z and changes the order or listing them to 100, 50, 20. -Page 5: VOA test. Under conditions column ...deleted "20mV to". It now reads ... Vsense = 100mV SR test. Under conditions column ..deleted what was there. It now reads ... Pulse on RS+pin, See Figure 15 -Page 6: ts test. Removed Gain = 100 and Gain = 100V/V in both description and conditions columns respectively. -Page 9 Added Figure 15 and adjusted figure numbers to account for the added figure. Initial Release
4/12/10 4/7/10
2/3/10
12/14/09
FN6973.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28005 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6973.3 September 16, 2010
ISL28005
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10
1.90 D A 5 4 0-3 0.08-0.20
PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 2 0.95 SEE DETAIL X B 0.40 0.05 3 END VIEW 0.20 C 2x 5 (0.60)
0.20 M C A-B D TOP VIEW 10 TYP (2 PLCS)
2.90
5
0.15 C A-B 2x C 1.14 0.15 0.10 C SEATING PLANE 1.45 MAX
H
(0.25) GAUGE PLANE
SIDE VIEW
0.05-0.15 DETAIL "X" (0.60)
0.450.1
4
(1.20) NOTES: (2.40) 1. 2. 3. 4. 5. 6. (0.95) (1.90) TYPICAL RECOMMENDED LAND PATTERN Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5M-1994. Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. This dimension is measured at Datum "H". Package conforms to JEDEC MO-178AA.
14
FN6973.3 September 16, 2010

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